TSMC HPC Business 1Q26 Revenue Momentum and Advanced Capacity In-Depth Analysis Report

I. 1Q26 Revenue QoQ Growth Breakdown and Customer Shifts

The growth in 1Q26 reflects a structural shift where capacity is highly concentrated in high-margin AI applications. The revenue increments are predominantly centralized around the leading AI accelerator provider and the ASIC supply chains of specific cloud giants.

• Nvidia Remains the Core Growth Engine: Nvidia's single-quarter revenue contribution is estimated to jump significantly from the USD 5.5-6.0 billion range in 4Q25 to the USD 6.5-7.0 billion range in 1Q26 (an increase of approximately USD 1 billion). By securing massive advanced process and packaging capacity, coupled with hot-run premiums, Nvidia maintains an extremely high Average Selling Price (ASP), contributing substantially to TSMC's gross margins.

• Explosive Growth in Cloud ASICs: The Google TPU supply chain is demonstrating astonishing momentum. Core foundry partner Broadcom's revenue is expected to double from USD 400-500 million in 4Q25 to nearly USD 1 billion in 1Q26. Benefiting from a dual-supplier strategy, MediaTek's revenue is also projected to double from nearly USD 200 million to the USD 300-400 million range, as they prepare for large-scale project rollouts in the second half of the year.

• AWS Procurement Strategy Shift: AWS is shifting toward a direct procurement model, and its in-house Trainium chips are entering a new stocking cycle. Annapurna's revenue contribution is estimated to surge from roughly USD 200 million to over USD 550 million. Key partner Alchip is also expected to see a leap from about USD 100 million to over USD 300 million.

• Customer Dynamics Under Capacity Reallocation: With booming AI demand, TSMC has proactively reduced quotas for low-margin customers. Bitmain's revenue will drop sharply from USD 1.5 billion to around USD 1 billion. Apple and Qualcomm will see slight revenue pullbacks due to seasonal slumps and market headwinds, respectively. Meanwhile, AMD (USD 2.6-2.8 billion) and Intel (around USD 20 billion) will maintain high-level consolidation and steady growth.

II. Flagship AI Accelerator Shipment Rhythm and CoWoS Capacity Allocation

Front-end wafer starts rely heavily on back-end CoWoS capacity to translate into actual shipments. The capacity allocation in 1Q26 is experiencing intense generational transitions and technical bottlenecks.

• Nvidia's Generational Transition: The B300 has become the stabilizing cornerstone, with single-quarter CoWoS demand reaching roughly 90,000 to 110,000 wafers, while transitional products like the B300A will gradually phase out. The next-generation Rubin (R100) is expected to generate an initial demand of several thousand CoWoS-L wafers. To maintain stable supply during this transition, Nvidia may slightly increase its Blackwell wafer starts.

• Google TPU's CoWoS-S Bottleneck: TPU projects heavily rely on older CoWoS-S technology, which has a monthly capacity ceiling of about 18,000 to 19,000 wafers. This bottleneck has led to a backlog of over 3 million unpackaged front-end chips. To satisfy the strong TPU demand, TSMC has temporarily delayed plans to convert certain fabs to newer technologies. Broadcom's TPU v7 projects alone could consume nearly 20,000 wafers of capacity in 1Q26.

• Consumer GPUs Permanently Yielding to AI: Due to soaring HBM and GDDR memory costs squeezing consumer-end margins, Nvidia has slashed wafer starts for mid-to-high-end consumer GPUs (by nearly 10%). This capacity has been irreversibly transferred to high-margin AI and data center applications, further elevating the overall HPC ASP.

III. Expansion Limits of Advanced Nodes (3nm/2nm) and Long-Cycle Phenomenon

The relentless pursuit of extreme transistor density and power efficiency for AI chips has triggered structural capacity shortages in the 3nm and 2nm nodes.

• 3nm Structural Shortage and Extreme Concentration: Fab 18 Phase 9 in Tainan will be the last newly built 3nm fab in Taiwan; future capacity additions will shift to Fab 21 in the US. By 2027, Nvidia's next-generation products and AWS's Trainium 3 deployments alone are highly likely to consume 70% to 80% of the total 3nm capacity, indicating an unprecedented level of shortage.

• 2nm Mass Production Challenges and the Long-Tail Effect: The 2nm node is projected to reach 90,000 wafers per month by late 2025 and 140,000 by late 2026, though it faces initial technological and yield challenges. Because 2nm costs are exorbitant and 3nm capacity is intentionally kept tight by TSMC, the product life cycles for both 3nm and 2nm in the HPC sector are expected to extend significantly, ensuring TSMC maintains excellent capacity utilization and profitability for years to come.

IV. Conclusion and Future Outlook

TSMC's projected USD 20 billion HPC revenue in 1Q26 reveals a shift in the semiconductor industry's underlying logic: revenue momentum is now driven by a dual-engine of "Nvidia" and the "Cloud ASIC Camp." By precisely allocating resources, TSMC has funneled its precious advanced nodes and packaging capacity exclusively to AI giants capable of absorbing hot-run premiums, establishing a near-monopoly seller's market and exhibiting immense pricing power.